Agenda

CONFERENCE ORGANIZERS

General Chair
Philip Garrou
Microelectronic Consultants of NC

Technical Co-chair – Asia
Mitsumasa Koyanagi
Tohoku University

Technical Co-chair – Europe
Mark Scannell
CEA-Leti

3D ASIP has been recognized as the premier conference on 2.5 / 3DIC focused on commercialization and infrastructure and in 2017 is expanding to cover all HIGH DENSITY 3D PACKAGING SOLUTIONS. Continuing the tradition of offering cutting-edge presentations from scientists, technologists and business leaders from across the globe.

Registration to participate in 3D ASIP 2017 will open this Spring. 3DASIP2017_Sponsorship & Exhibit opportunities are now available!

The 2017 3D ASIP Conference opens with morning tutorial sessions on Tuesday, December 5. John Hunt of ASE is confirmed with a course on FOWLP. Other tutorials announced this Spring.

The general conference sessions follow on Tuesday afternoon, Wednesday and Thursday, December 5-7. Once again presentations will be by invitation only. Current plans are to have  7 sessions (30+ presentations) and 5 Keynote talks. The following 7 session topics are currently being suggested (4-5 presentations each):

1. 2.5/3D enabled applications
2. Micro bump and copper pillar technology
3. FOWLP
4. Defense and Aerospace
5.  Micro Assembly and Dicing
6. Image sensors
7.  Equipment & Materials

KEYNOTE 1 – Jim Walker – Gartner has accepted and will discuss state of the IC industry
Additional Keynotes to be announced soon.

 

Additional Details for 2017 3D ASIP Soon

*******

THANK YOU TO THE 2016 PLATINUM SPONSOR:EVGGS

 

Tuesday, December 13, 2016

7:30am-6:30pm Registration Open
8:00am-8:45am Breakfast
12:00pm-7:00pm Exhibits Open (when not in session)
10:30 – 10:45 a.m. Break
9:00am-12:00pm PRE-CONFERENCE TUTORIAL – Option 1:  Advances in Fan-Out Wafer Level Packaging

Abstract: Now that Fan-out wafer level packaging (FO-WLP) has matured, unique advanced FO-WLP structures have been developed. This course will cover these advanced structures of FO-WLP and potential application spaces, technology roadmaps, and benchmarking. The challenges of moving from 300mm FO-WLP to panel will also be discussed.

1.              Definitions and Advantages
2.              Advanced Applications
3.              Package Structures including Advanced FO technologies
4.              Technology Roadmap
5.              Panel Challenges
6.              Benchmarking

Engineers and managers responsible for advanced packaging development, package characterization, package quality, package reliability and package design should attend this course. Engineers and those in marketing and sales who supply equipment, materials, or services to the advanced packaging supply chain should also attend. Both newcomers and experienced practitioners are welcome, but it is recommended that you take the Introduction to Fan-Out Wafer Level Packaging course prior to taking this course.

Beth Keser, Qualcomm |  Beth is a recognized global leader in the semiconductor packaging industry with over 18 years of experience, received her B.S. degree in Materials Science and Engineering from Cornell University and her Ph.D. from the University of Illinois at Urbana-Champaign. Beth’s excellence in developing revolutionary electronic packages for semiconductor devices has resulted in 14 patents, 9 patents pending, and over 40 publications in the semiconductor industry. Based in San Diego, Beth leads the Fan-Out and Fan-In Wafer Level Packaging Technology Development and NPI Group at Qualcomm. Beth’s team has qualified over 50 products resulting in over 6 billion units shipped–technology consumers around the world enjoy in cell phones today. Beth is also an IEEE CPMT Distinguished Lecturer who chaired IEEE CPMT’s 2015 Electronic Component and Technology Conference.

9:00am-12:00pm PRE-CONFERENCE TUTORIAL – Option 2:  Electrical Modeling & Test Strategies for 3D Packages

Abstract: Today’s miniaturization and performance requirements result in the usage of high-density advanced packaging technologies, such as system-in-package (SIP), direct-chip-attach, chip-scale packaging (CSP), and ball-grid-arrays (BGA). Due to their physical access limitation, the complexity and cost associated with their test and diagnosis are considered major issues facing their use.

This course introduces comprehensive knowledge of electrical modeling and test solutions for 3D packages. We begin by a short tutorial on 3D packages including interposers and TSV. We then place particular emphasis on electrical modeling; test and debugging approaches for 3D packages for RF, bio, power and MEMS packages. Finally, we cover diagnosis and repair techniques for assembled packages.

Bruce Kim, City University of New York | Bruce is a professor of the Department of Electrical Engineering at City University of New York. He has about 300 publications in packaging and testing areas. He has instructed previous PDCs at IMAPS, IEEE EPTC and ECTC conferences. He is a Fellow of IMAPS and received the IMAPS Outstanding Educator award in 2012. He has also been a student chapter advisor. His research interests are in 3D passive components modeling and testing.

12:00pm-12:45pm Lunch

Sponsored by:
SussGS

1:00pm-1:15pm Welcome & Opening Remarks – Conference Co-Chairs:  Alan Huffman, Micross Advanced Interconnect Technology;
Prof. Mitsu Koyanagi, Tohoku University;
Mark Scannell, CEA-Leti
 SESSION 1 PLENARY SESSION – KEYNOTE 
1:15pm-2:00pm  Image Sensor Technology Evolution for Sensing Era
Tetsuo Nomoto, Sony Semiconductor Solutions
SESSION 2 2.5 / 3D ENABLED APPLICATIONS
Session Chair: Urmi Ray, Qualcomm
2:00pm-2:20pm 2.5D and System in Package
Rich Rice, ASE
2:20pm-2:40pm 2.5 & 3D Integrated Opto Sensors
Franz Schrank, amsAG
2:40pm-3:00pm 3DVLSI: The Emerging 3D SOC Technologies of the Future
Yang Du, Qualcomm
3:00pm-3:40pm Coffee Break in the Exhibit Area 

Sponsored by:
Amkor logo - blue 200p wide

3:40pm-4:00pm Next Generation Multi-Die IC Packaging – 2.5D, 3D and Beyond
Mike Kelly, Amkor Technology
4:00pm-4:20pm Quilt Packaging
Jason Kulick, Indiana IC
SESSION 3 MEMORY STACKS AND APPLICATIONS
Session Chair: Bob Patti, Tezzaron
4:20pm-4:40pm Memory Packaging Overview
Emilie Jolivet, Yole Développement
4:40-pm-5:00pm Demystifying 2.5D ASIC Production
Mike Gianfagna, Patrick Soheili, eSilicon Corporation
5:00pm-5:20pm Evolving Memory
Bob Patti, Tezzaron
5:20pm-5:40pm Fabrication and Reliability of Fine RDL Structure Patterned by Excimer Laser
Habib Hichri, SUSS MicroTec Photonic Systems
5:40pm-7:00pm WELCOME RECEPTION IN THE EXHIBIT AREA 

Sponsored by:
EVGGS

 

 


Wednesday, December 14, 2016

7:00am-7:00pm Registration Open
7:00am-8:00am Breakfast

Sponsored by:
SussGS

10:00am-7:00pm Exhibits Open (when not in session)
8:00am-8:15am Opening Remarks – Conference Co-Chairs:Alan Huffman, Micross Advanced Interconnect Technology;
Prof. Mitsu Koyanagi, Tohoku University;
Mark Scannell, CEA-Leti
SESSION 4 PLENARY SESSION – KEYNOTE
8:15am-9:00am Future Landscapes for 3D Integration: From Interposers to 3D High Density
Jean  Michailos, STMicroelectronics
SESSION 5 IMAGE SENSOR TECHNOLOGY
   Session Chair: Paul Enquist, Tessera
9:00am-9:20am 3D Stacked Image Sensors from a Chinese Perspective
Roc Blumenthal, SMIC
9:20am-9:40am Advanced Image Sensors through the use of Wafer Stacking
Roger Panicacci, ON Semiconductor / Aptina (Hans Stork)
9:40am-10:00am 3D Integrated Sensors: Options for the Fabless
Barmak Mansoorian, Forza Silicon
10:00am-10:40am Coffee Break in the Exhibit Area 

Sponsored by:
Amkor logo - blue 200p wide

10:40am-11:00am Raytheon Large Format SiPIN Hybrid Visible Imaging Arrays
Sean Kilcyone, Raytheon
11:00am-11:20am CMOS Image Sensor Evolution by Direct Bond Technology
Paul Enquist, Tessera
SESSION 6 PLENARY SESSION – KEYNOTE
11:20am-12:05pm The Heterogeneous Integration Roadmap
Bill Chen, ASE
12:00pm-1:15pm Lunch & Exhibition

Sponsored by:

SESSION 7 PLENARY SESSION – KEYNOTE
1:15pm-2:00pm  Heterogeneous SoCs
Professor Subramanian Iyer, UCLA
SESSION 8 MILITARY & AEROSPACE
  Session Chair: Philip Garrou, Microelectronic Consultants of NC
2:00pm-2:20pm Digital Interface Standards for 2.5D Heterogeneous Integration for DoD Applications
Tim Lee, Boeing (Hsuanyu “Marcus” Pan)
2:20pm-2:40pm Advanced III-V and CMOS DAHI Integration Technology
Augusto Gutierrez-Aitken, Northrop Grumman
2:40pm-3:00pm 3D Heterogeneous Integration of CMOS, InP, and GaN Devices Using Hybrid Wafer Bonding
Andrew Carter, Teledyne
3:00pm-3:40pm Coffee Break in the Exhibit Area 

Sponsored by:

3:40pm-4:00pm Enabling Cost Effective IP Reuse with 2.5/3D Integration
Yuan Xie, UC Santa Barbara
4:00pm-4:20pm C-Band Digital Power Amplifier in DAHI Technology
Brian Dupaix, Ohio State University
SESSION 9 EQUIPMENT AND MATERIALS
  Session Chair: Markus Wimplinger, EV Group
4:20pm-4:40pm Thin Wafer Plasma Dicing Challenges
Brad Eaton, Applied Materials
4:40-pm-5:00pm Temporary Wafer Bonding Technology for Advanced Packaging
Dongshun Bai, Brewer Science
5:00pm-5:20pm Some Essentials of Thermo-Compression Bonding
Hugo Pristauz, BESI
5:20pm-5:40pm Extreme Wafer Thinning to 5 µm for Low Cost Via Last
Dave Thomas, SPTS
5:40pm-6:00pm Bonding Technologies for High Performance and High Bandwidth Applications
Thomas Uhrmann, EV Group
6:00pm-7:00pm EXHIBIT HALL RECEPTION 

Sponsored by:

 

 


Thursday, December 15, 2016

7:00am-12:00pm Registration Open
7:00am-8:00am Breakfast
8:00am-8:15am Opening Remarks – Conference Co-Chairs:  Alan Huffman, Micross Advanced Interconnect Technology;
Prof. Mitsu Koyanagi, Tohoku University;
Mark Scannell, CEA-Leti
SESSION 10 FAN OUT AND OTHER COMPETITIVE TECHNOLOGIES
Session Chair: Beth Keser, Qualcomm
8:15am-8:35am Path to the Fan-out SoC
Tim Olson, DECA Technologies (Craig Bishop)
8:35am-8:55am Fan-out – An Optimal Package Solution to Enable Thin Mobile and Wearable
Albert Lan, SPIL
8:55am-9:15am The Tao to 3D SiP
John Hunt, ASE
SESSION 11 DESIGN
 Session Chair: Pascal Vivet, CEA-Leti
9:15am-9:35am Why and how Multi-die ICs and Advanced Packaging (2.5D, 3D, WLP) Broaden the Market for Traditional SoCs
Herb Reiter, EDA2ASIC
9:35am-9:55am Impact of 3D Integration in the IC Design-Manufacturing Interface
Juan Rey, Mentor Graphics
9:55am-10:15am Chiplet Partitioning for 3D Manycore Architectures
Denis Dutoit, CEA-Leti
10:15am-11:00am Coffee Break in the Foyer 

Sponsored by:

SESSION 12 Status of Glass Technology for High Density Packaging
   Session Chair: Aric Shorey, Corning
11:00am-11:20am Glass as the Next Generation IC Packaging Platform
Yu-Hua Chen, Unimicron
11:20am-11:40am Direct Metallization on Glass Using a Metal Oxide Adhesion Promoter for Glass Substrates / Interposers
Michael Merschky, Atotech
11:40am-12:00pm Glass Core Technology: Leveraging Glass and Lasers for Advanced Packaging
Roupen Keusseyan, Samtech
12:00pm-12:20pm Advances in Glass Packaging
Aric Shorey, Corning
12:20pm Closing Remarks