Agenda

CONFERENCE ORGANIZERS

Technical Chair
Alan Huffman
RTI

Program Coordinator & Past Chair
Philip Garrou
Microelectronic Consultants of NC

Technical Co-chair – Asia
Mitsumasa Koyanagi
Tohoku University

Technical Co-chair – Europe
Mark Scannell
LETI

The 2016 3D ASIP Conference opens with morning tutorial sessions on Tuesday, December 13. The general conference sessions follow on Tuesday afternoon, Wednesday and Thursday, December 13-15.

Sessions will be formed and speakers invited along the following topical areas with champions identified to recruit key companies/experts in these areas:

1. Image sensors – Paul Enquist – Ziptronix (Invensas)
2. Equipment & Materials – Markus Wimplinger – EVG
3. Glass – Aric Shorey – Corning
4. Memory stacks & applications – Bob Patti – Tezzaron
5. 2.5 / 3D enabled Applications – Umi Ray – Qualcomm
6. Fan out & other competitive technologies – Beth Keser – Qualcomm
7. Military and Aerospace – Jeff Demmin – Booz Allen Hamilton
8. Design – Pascal Vivet – CEA Leti

We will  have 1 plenary/keynote speaker from each geographical region as well:

  • USA:  Subu Iyer, UCLA/IBM: CHIPS – Center for Heterogeneous Integration and Performance Scaling
  • Europe:  Jean Michailos, ST Micro: Title TBD
  • Asia:  Tetsuo Nemoto, Sony Semiconductor Solutions Corp.: Image Sensor Technology Evolution for Sensing Era

 

The committee is finalizing the program now – details soon.

 

The 2015 3DASIP agenda….

Tuesday, December 15, 2015

TUTORIAL: TEMPORARY BONDING / DEBONDING PROCESSES, MATERIALS, AND EQUIPMENT
8:30 – 9:00 a.m. Overview of Temporary Wafer Bonding for 3D Integration
Moderator: Matt Lueck, Research Engineer, RTI International
 9:00 – 9:30 a.m. Temporary Wafer Bonding and Debonding:
Processes, Materials, and Equipment
Frank Fournel, Head of Bonding Technology Engineering, CEA-Leti
9:30 – 10:00 a.m. Thin Wafer Handling:  Methods and Challenges
Molly Hladik, Principal Applications Engineer, Brewer Science
10:00 – 10:30 a.m. Polyimide Wafer Bonding Adhesives for 2.5D and 3D Packaging
Melvin Zussman, Principal Investigator, HD MicroSystems
10:30 – 10:45 a.m. Break
10:45 – 11:15 a.m. Temporary Bonding Solutions for 3D IC and Fan-Out WLP
Thomas Uhrmann, Director of Business Development, EV Group
11:15 – 11:45 a.m. Temporary Bonding and Debonding: Process, Material, and Equipment
Shoji Otaka, General Manager TOK
11:45 a.m.-12:15 p.m. Temporary Wafer Bonding and Debonding: Processes, Materials, and Equipment
Stefan Lutter, General Manager Bonder Division, SUSS MicroTec

12:15 p.m. Lunch (on your own)

TUTORIAL: 
DESIGN of ICs USING INTERPOSERS or WAFER-LEVEL PACKAGING
 1:00 – 1:10 p.m Welcome and Opening Remarks
Moderator: Herb Reiter, Consultant, eda2asic
1:10 – 1:30 p.m. Interposer Design and Its Impact on the System
Bill Isaacson, Director, Product Marketing, eSilicon
1:30 – 1:50 p.m. PDN Design Planning Utilizing a Path Finding Approach
Bill Martin, President, VP of Engineering, E-System Design
1:50 – 2:10 p.m. Verification of Power and Thermal Integrity for Large Vertically Stacked Dies
Norman Chang, VP & Sr. Product Strategist, Apache BU, ANSYS, Inc.
2:10 – 2:30 p.m. Integrated Flow for Silicon Interposer Based 2.5D-IC Realization
Brandon Wang, Group Director, Cadence Design Systems
2:30 – 2:50 p.m. Wafer Level CSP Challenges and Methodologies
Bill Acito, Product Engineer, Cadence Design Systems
2:50 – 3:10 p.m. Break
3:10 – 3:30 p.m. Improving Design Performance with System-level Co-design and Multi-physics Analysis
Narayanan Terizhandur Varadharajan, Solutions Architect, Zuken
3:30 – 5:25 p.m. Design Tool Considerations for 2.5D-IC’s & Multi-die packaging
John Ferguson, Director of Marketing, Mentor Graphics
and
John Park, Market Development Manager/ Methodology Architect, Mentor Graphics
5:25 – 5:30 p.m. Closing Remarks, Herb Reiter
6:00 – 8:00 p.m. Welcome Reception
Sponsored by Tezzaron

Wednesday, December 16, 2015

7:45 – 8:45 a.m. Registration and Continental Breakfast
Sponsored by SUSS MicroTec
8:45 a.m. Welcome/Opening Comments
Conference General Chair
Philip Garrou, IEEE Fellow and Consultant
Microelectronic Consultants of NC

SESSION 1:  PLENARY SESSION

9:00 a.m. Comparison of New Memory Architectures
Rozalia Beica, CTO
Yole Développement
9:45 a.m.
Status of 2.5/3D and Other High-Density Packaging Options
Brandon Prior, Senior Consultant
Prismark Partners
10:15 a.m. Networking Break

 

SESSION 2:  TSV-BASED MEMORY STACK PRODUCTS BECOME A REALITY

10:45 a.m. TSV Era in Memory
Minsuk Suh, Director
SK Hynix
11:15 a.m.
TSV Technology for NAND Flash Memory
Kazuyuki Higashi, Senior Research Scientist
Toshiba
11:45 a.m.
The Last Centimeter: Challenges in the Development and Deployment of Ultra High-Performance 3Di DRAM Systems
Thomas Gregorich, Vice President, Package Technology
Micron Technology
12:15 p.m. Tezzaron DiRAM4: Memory Architecture for Flexibility and Performance
Bob Patti, CTO
Tezzaron
12:45 p.m. Lunch Sponsored by Invensas

 

SESSION 3:  PRODUCTS & PRODUCTION IN THE 2.5/3D INFRASTRUCTURE

2:00 p.m.
Fiji AMD Module
Bryan Black, Senior AMD Fellow
AMD
2:20 p.m.
Rational 3-Dimensional Devices
Teruo Hirayama, SVP / President of Device & Material R&D Group, Sony
2:40 p.m. Enabling Next-Generation Platforms Using Altera’s Heterogenous 3D System-in-Package Technology
Arifur Rahman, System Planner
Altera Corporation
3:00 p.m. Inflections in Foundry Package Offerings
Rama Alapati, Director, Packaging Product Management
GLOBALFOUNDRIES
3:20 p.m. Networking Break
 

SESSION 4:  3D EQUIPMENT AND METROLOGY

3:45 p.m.
Bonding Technologies for High Volume 3D IC Manufacturing
Markus Wimplinger, Corporate Technology Development and IP Director
EV Group
4:05 p.m.
More Die, Stronger Die. Smaller and Thinner Packages Drive Die Singulation by Plasma Etch
David Butler, VP Marketing
SPTS Technologies
4:25 p.m.
Advances in Process Control Strategies for Wafer Level Packaging
Prashant Aji , Sr. Director of Marketing, KLA Tencor 
4:45 p.m. Fan-Out Packaging – An Abundance of Creative Options
Rajiv Roy, VP Business Development
Rudolph Technologies
6:00 – 8:00 p.m. Evening Reception Sponsored by EV Group

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Thursday, December 17

 

7:45 – 8:45 a.m. Registration and Continental Breakfast
 8:45 a.m. Opening Remarks and Award Presentation
Pioneer Award Recipients
Professor Mitsumasa Koyanagi, Tohoku University
Dr. Peter Ramm, Head of Department Heterogeneous System Integration, Fraunhofer EMFT


SESSION 5:  SPECIAL SESSION – FRONTIERS OF 3DIC

9:00 a.m. My Early Years in 3DIC
Mitsumasa Koyanagi, Professor
Tohoku University
9:30 a.m. Our Early and Our Ongoing Work in 3D Integration
Peter Ramm, Head of Department Heterogeneous System Integration
Fraunhofer EMFT

SESSION 6:  Alternate High Density Packaging Technology

10:00 a.m.
A TXV-less Solder-less and Underfill-less Packaging Platform for the Era of IoTs
Dyi-Chung Hu, Senior Executive Advisor
Unimicron
10:30 a.m. Networking Break

SESSION 7:  HIGH DENSITY PACKAGING WITHOUT TSV

10:45 a.m.
SLIT – A TSV‐Less Interconnect Technology
Suresh Ramalingam, Fellow
Xilinx
11:15 a.m. Amkor’s Next Generation Package Technologies: SLIM and SWIFT
Mike Kelly, Sr. Director, Advanced Package Development
Amkor Technology
11:45 p.m.
Simplified High Performance Integration Technology
Doug Yu, Senior Director Integrated Interconnect and Package Division, R&D
Taiwan Semiconductor Manufacturing Co.
12:15 p.m. Lunch

SESSION 8:  HETEROGENEOUS INTEGRATION

1:40 p.m.
DARPA’s Heterogeneous Integration Vision and Progress on Modular Design
Dan Green, Program Manager
DARPA
2:00 p.m.
DAHI Integration Technology at Northrop Grumman Aerospace Systems
Augusto Gutierrez-Aitken, NG Technical Fellow/ DARPA DAHI Program PI
Northrup Grumman Aerospace Systems
2:20 p.m. 3D Heterogeneous Integration of III-V Devices and Si CMOS
Miguel Urteaga, Manager, Advanced Material and Devices Department, Electronics Division
Teledyne
2:40 p.m. Heterogeneous Integration of Microdevices by Transfer Printing
Chris Bower, Chief Technology Officer
X-Celeprint
3:00 p.m. Networking Break

SESSION 9:  DESIGN AND MISCELLANEOUS

3:30 p.m.
Advanced Packaging and Interconnect Options for Heterogeneous Integration
John Lannon, Senior Research Engineer
RTI International
3:50 p.m. Fan-Out Wafer Level Packaging; A Layout and Verification Guide
John Ferguson, Marketing Director, Mentor Graphics 
4:10 p.m. Liquid Process Low-k Oxides: Potential for Packaging Applications?
Hash Pakbaz, SBA Materials 
4:30 p.m. Closing Remarks
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