Agenda

CONFERENCE ORGANIZERS

General Chair
Philip Garrou
Microelectronic Consultants of NC

Technical Co-chair – Asia
Mitsumasa Koyanagi
Tohoku University

Technical Co-chair – Europe
Mark Scannell
CEA-Leti

3D ASIP has been recognized as the premier conference on 2.5 / 3DIC focused on commercialization and infrastructure and in 2017 is expanding to cover all HIGH DENSITY 3D PACKAGING SOLUTIONS. Continuing the tradition of offering cutting-edge presentations from scientists, technologists and business leaders from across the globe.

Registration to participate in 3D ASIP 2017 will open this Spring. 3DASIP2017_Sponsorship & Exhibit opportunities are now available!

The 2017 3D ASIP Conference opens with morning tutorial sessions on Tuesday, December 5. The general conference sessions follow on Tuesday afternoon, Wednesday and Thursday, December 5-7. All of the speaker presentations for 3D ASIP 2017 have been  by invitation only.

THANK YOU TO THE 2017 PLATINUM SPONSOR:EVGGS

 

Tuesday, December 5, 2017

7:30am-7:00pm Registration Open
8:00am-8:45am Breakfast
12:00pm-7:00pm Exhibits Open (when not in session)
10:30 – 10:45 a.m. Break
9:00am-12:00pm

 

(Select 1 of the 3 Tutorials only ** Tutorials an additional fee to conference registration during checkout)

Pre-Conference Tutorials Run 9am-12pm the first morning. You may select one of the Tutorials only: Evolution of High Density Packaging; Fan Out Packaging Evolution & Complexity; OR Introduction to Solder Flip Chip with an Emphasis on Cu Pillar. Tutorials are available for an additional fee from the regular conference registration. Descriptions of the courses are below, and you may select a tutorial during CHECKOUT (on the “sessions” page).

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PRE-CONFERENCE TUTORIAL – Option 1: 

The Evolution of High Density Packaging

**THIS TUTORIAL IS 2-HOURS – 9am-11am**

Abstract:

1. Microelectronic Packaging Platforms
-Function & Early History of Packaging
​-Peripheral Leaded packages
​-Area array Packaging
​-BGA packaging
​-Bumping/ FC
-Redistribution, UBM, Underfill
​-Wafer level Packaging (WLP)
​-Copper pillar bump
​-Embedded packaging ( molded fan out vs laminate embedded)
-Chips vs RDL first
​-3D packaging (Stacked WB, Package on package, 3DIC)

2. Microelectronics Market & Business Considerations
-Markets and Applications
​-The future of scaling
-Consolidation and Business Issues

3. Where is Packaging Technology Going

Phil Garrou, Microelectronic Consultants of NC | Dr. Philip Garrou retired from Dow Chemical in 2004 as Global Director of Technology for their Advanced  Electronic Materials business unit. He is now contributing editor and blogger  (“Insights from the Leading Edge”) for Solid State Technology , a subject matter expert (SME) for DARPA and runs his consulting company Microelectronic Consultants of NC in the RTP area.

PRE-CONFERENCE TUTORIAL – Option 2: 

Fan Out Packaging Evolution & Complexity

Abstract:

With the ubiquitous use of a wide variety of mobile devices, along with the rise of the Internet of Things, the Electronics industry has been driven by the need for a continual reduction in the thickness and physical volume of semiconductor packaging. Fan Out technology has evolved as an alternative package to answer this need for miniaturization of electronics, while also providing improved electrical interconnectivity.

At the same time, the wide use of mobile devices and the newer IOTs has driven the need for increased capability of data centers, and Fan Out technology is finding value in the heterogeneous integration of die and memory with improved electrical performance, with lower cost than traditional 2.5 packaging for these data center requirements.

We will review how the integration of wafer level processing technologies; substrate evolution and Flip Chip packaging structures have come together into what is being called Fan Out Packaging. These packages are for both low density and high density, Mobile and server applications. They have higher levels of integration and sophistication than has ever been possible in the past. An overview of the concept of Fan Out packaging, a history of its evolution, both low end and high end applications, and market trends will be included in this course.

John Hunt, ASE US, Inc. | John is Senior Director, Engineering, Technical Promotion, at ASE US Inc., and provides technical support for the Introduction, Engineering, Marketing, and Business Development activities for Advanced Wafer Level and Fan Out Packaging Technologies at ASE.

John has more than 40 years of experience in various areas of manufacturing, assembly and testing of electronic components and systems, with emphasis on the development of new technologies and processes, with a B.S. from Rutgers and an M.S. from University of Central Florida.

PRE-CONFERENCE TUTORIAL – Option 3:

Introduction to Solder Flip Chip with an Emphasis on Cu Pillar

*THIS COURSE WAS CANCELLED*

 

12:00pm-1:00pm Lunch         (Exhibits Open)

Sponsored by:
SussGS

1:00pm-1:15pm Welcome & Opening Remarks – Conference Co-Chairs:  Phil Garrou, Microelectronic Consultants of NC; Prof. Mitsu Koyanagi, Tohoku University; and Mark Scannell, CEA-Leti
 SESSION 1 PLENARY SESSION – KEYNOTE: 
1:15pm-2:00pm World Level Packaging Concepts “Wafer, Wafer – Who’s Got The Wafer?”
Jim Walker, WLP Concepts
SESSION 2 MICRO BUMPING AND COPPER PILLAR TECHNOLOGY
Session Chair: Alan Huffman, Micross
2:00pm-2:20pm Fine Pitch Cu Pillar Bond on Lead Assembly
Hyunil Bae,  STATSChipPAC
2:20pm-2:40pm New Requirements for Productivity and Accuracy in   HVM Memory Stacking
Tom Strothmann, Kulicke & Soffa Industries
2:40pm-3:00pm Microbump DAHI Technology for integration of Compound Semiconductors to CMOS
Augusto Gutierrez-Aitken, Northrop Grumman
3:00pm-3:20pm High Density Interconnect Bonding at 10 um Pitch and Below Using Non-Collapsible Microbumps
Matt Lueck, Micross
3:20pm-4:00pm
Coffee Break in the Exhibit Area 

Sponsored by:
Amkor logo - blue 200p wide

SESSION 3 EQUIPMENT & MATERIALS
Session Chair: Markus Wimplinger, EV Group
4:00pm-4:20pm Advanced Materials and Interconnect Technologies for 3D Packaging
Rozalia Beica, Dow Electronic Materials
4:20-pm-4:40pm TSV, FOWLP, Hybrid Bonding : Review of Metrology Challenges and Solutions to Support HVM
Gilles Fresquet, Unity SC
4:40pm-5:00pm Equipment & Process Solutions for Heterogenous Integration
Thomas Uhrmann, EV Group
5:00pm-5:20pm The Evolution of Substrate Build-up and Thin Wafer Handling
Kim Yess, Brewer Science
5:20pm-5:40pm  From Image Sensors to Everything, A New Architecture
Javier DeLaCruz, Xperi
5:40pm-7:00pm WELCOME RECEPTION IN THE EXHIBIT AREA 

Sponsored by:
EVGGS

 


Wednesday, December 6, 2017

7:00am-7:00pm Registration Open
7:00am-8:00am Breakfast

Sponsored by:
SussGS

10:00am-7:00pm Exhibits Open (when not in session)
8:00am-8:15am Opening Remarks – Conference Co-Chairs: Phil Garrou, Microelectronic Consultants of NC;
Prof. Mitsu Koyanagi, Tohoku University;
Mark Scannell, CEA-Leti
SESSION 4 PLENARY SESSION – KEYNOTE
8:15am-9:00am High Density Interconnects: Migrating from Concept to Mainstream
Brandon Prior, Prismark
SESSION 5 2.5/3D ENABLED APPLICATIONS
   Session Chair: Suresh Ramalingham, Xilinx
9:00am-9:20am 2.5D and 3D for Sensor Integration
Franz Schrank, amsAG
9:20am-9:40am HBM Test Challenges in 2.5D ASIC/SiP
Krishnamoorthy Balachandran, Cisco
9:40am-10:00am TSV Integrated Technologies
Hamid Eslampour, GlobalFoundries
10:00am-10:40am Coffee Break in the Exhibit Area 

Sponsored by:
Amkor logo - blue 200p wide

10:40am-11:00am Past, Present and Future Challenges of Thermal Management of Electronics Packaging
Gamal Refai-Ahmed, Xilinx
11:00am-11:20am Heterogeneous Platform: Innovation with Partners
Sergey Shumarayev, Intel
SESSION 6 PLENARY SESSION – KEYNOTE
11:20am-12:05pm Impact of Design on Advanced Packaging
Juan Rey, Mentor, a Siemens Business
12:00pm-1:15pm Lunch 

Sponsored by:

available for sponsorship 

SESSION 7 PLENARY SESSION – KEYNOTE
1:15pm-2:00pm CHIPS
Dan Green, DARPA MTO
SESSION 8 MILITARY & AEROSPACE
  Session Chair: Jeff Demmin, Booz Allen
2:00pm-2:20pm Disaggregation of Advanced Node SoCs into 2.5D Modular Architectures for Rapid IP Reuse
Pavel Borodulin, Northrop Grumman
2:20pm-2:40pm Modular Interposer-based System Design Using a Flexible High-speed Interface
Zhengya Zhang, University of Michigan
2:40pm-3:00pm An Application Specific IP (ASIP) Approach Offers a Design Solution Between ASICs and FPGAs
Rick Stevens, Lockheed Martin
3:00pm-3:20pm Heterogeneous Integration Platform
Sergey Shumarayev, Intel
3:20pm-3:40pm Heterogeneous Integration of Modular Intellectual Property Strategies (HI-MIPS) Overview
Tim Lee, Boeing
3:40pm-4:20pm Coffee Break in the Exhibit Area 

Sponsored by:
Sponsorship Available

SESSION 9 ADVANCED ASSEMBLY TECHNOLOGY
  Session Chair: Chris Bower, X-Celeprint
4:20pm-4:40pm How to Peel Ultra Thin Dies from Wafer Tape
Stefan Behler, Besi Switzerland AG
4:40-pm-5:00pm New 2.5 / 3D Assembly based on Micro-scale Assembly
Mitsumasa Koyanagi,  Tohoku University
5:00pm-5:20pm Microtransfer Printing of High Performance InP HBTs to GaAs, Si and SiC Substrates
Andy Carter, Miguel Urteaga, Teledyne Scientific & Imaging
5:20pm-5:40pm Mass Transfer of Microscale Devices using Elastomer Stamps
Kanchan Ghosal, X-Celeprint
5:40pm-6:00pm Microassembly Printer
Eugene Chow, PARC
6:00pm-7:00pm EXHIBIT HALL RECEPTION 

Sponsored by:
Sponsorship Available

 


Thursday, December 7, 2017

7:00am-12:00pm Registration Open
7:00am-8:00am Breakfast
8:00am-8:15am Opening Remarks – Conference Co-Chairs:  Phil Garrou, Microelectronic Consultants of NC; Prof. Mitsu Koyanagi, Tohoku University; Mark Scannell, CEA-Leti
SESSION 10 PLENARY SESSION – KEYNOTE
8:15am-9:00am InFO
Doug Yu, TSMC
SESSION 11 FAN OUT WAFER LEVEL PACKAGING (FOWLP)
Session Chair: John Hunt, ASE US
9:00am-9:20am Enabling the Fan Out SiP
Chris Scanlan, DECA
9:20am-9:40am Wafer Fan Out – What does the Future Hold?
Ron Huemoeller, Amkor Technology
9:40am-10:00am Fan Out Packaging for High Frequency – What’s Ahead?
Vinayak Pandey, STATSChipPAC / JCET
10:00am-10:20am
Overview of Localized High-Density Embedded Interconnect: Variations and Practitioners
Mike Skinner, Intel


10:20am-10:40am Coffee Break in the Foyer 

Sponsored by:
Sponsorship Available

SESSION 12 IMAGE SENSOR TECHNOLOGY
   Session Chair: Hughes Metras, CEA-Leti
10:40am-11:00am
A Stacked CMOS Image Sensor with Array Parallel ADC Architecture for Region Control
Hayato Wakabayashi, Sony
11:00am-11:20am
Applications of 3D Stacked Image Sensor to High Speed Capturing, Broad Band Sensing and Global Shutter
Yoshiaki Takemoto, Olympus
11:20am-11:40am Advanced 3D Technologies for Smart Image Sensors
Severine Cheramy, CEA-Leti
11:40am Closing Remarks