Thursday, December 7, 2017

7:00am-12:00pm Registration Open
7:00am-8:00am Breakfast
8:00am-8:15am Opening Remarks – Conference Co-Chairs:  Phil Garrou, Microelectronic Consultants of NC; Prof. Mitsu Koyanagi, Tohoku University; Mark Scannell, CEA-Leti
SESSION 10 PLENARY SESSION – KEYNOTE
8:15am-9:00am InFO
Doug Yu, TSMC
SESSION 11 FAN OUT WAFER LEVEL PACKAGING (FOWLP)
Session Chair: John Hunt, ASE US
9:00am-9:20am Enabling the Fan Out SiP
Chris Scanlan, DECA
9:20am-9:40am Wafer Fan Out – What does the Future Hold?
Ron Huemoeller, Amkor Technology
9:40am-10:00am Fan Out Packaging for High Frequency – What’s Ahead?
Vinayak Pandey, STATSChipPAC / JCET
10:00am-10:20am
Overview of Localized High-Density Embedded Interconnect: Variations and Practitioners
Mike Skinner, Intel


10:20am-10:40am Coffee Break in the Foyer 

Sponsored by:
Sponsorship Available

SESSION 12 IMAGE SENSOR TECHNOLOGY
   Session Chair: Hughes Metras, CEA-Leti
10:40am-11:00am
A Stacked CMOS Image Sensor with Array Parallel ADC Architecture for Region Control
Hayato Wakabayashi, Sony
11:00am-11:20am
Applications of 3D Stacked Image Sensor to High Speed Capturing, Broad Band Sensing and Global Shutter
Yoshiaki Takemoto, Olympus
11:20am-11:40am Advanced 3D Technologies for Smart Image Sensors
Severine Cheramy, CEA-Leti
11:40am Closing Remarks

 

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