2017 Tutorial Speakers
Tutorial – Option 1: The Evolution of High Density Packaging
Tuesday, December 5| *NEW TIME* 9:00am-11:00am
1. Microelectronic Packaging Platforms
-Function & Early History of Packaging
-Peripheral Leaded packages
-Area array Packaging
-Redistribution, UBM, Underfill
-Wafer level Packaging (WLP)
-Copper pillar bump
-Embedded packaging ( molded fan out vs laminate embedded)
-Chips vs RDL first
-3D packaging (Stacked WB, Package on package, 3DIC)
2. Microelectronics Market & Business Considerations
-Markets and Applications
-The future of scaling
-Consolidation and Business Issues
3. Where is Packaging Technology Going
Phil Garrou, Microelectronic Consultants of NC | Dr. Philip Garrou retired from Dow Chemical in 2004 as Global Director of Technology for their Advanced Electronic Materials business unit. He is now contributing editor and blogger (“Insights from the Leading Edge”) for Solid State Technology , a subject matter expert (SME) for DARPA and runs his consulting company Microelectronic Consultants of NC in the RTP area.
Tutorial – Option 2: Fan Out Packaging Evolution & Complexity
Tuesday, December 5| 9:00am-12:00pm
With the ubiquitous use of a wide variety of mobile devices, along with the rise of the Internet of Things, the Electronics industry has been driven by the need for a continual reduction in the thickness and physical volume of semiconductor packaging. Fan Out technology has evolved as an alternative package to answer this need for miniaturization of electronics, while also providing improved electrical interconnectivity.
At the same time, the wide use of mobile devices and the newer IOTs has driven the need for increased capability of data centers, and Fan Out technology is finding value in the heterogeneous integration of die and memory with improved electrical performance, with lower cost than traditional 2.5 packaging for these data center requirements.
We will review how the integration of wafer level processing technologies; substrate evolution and Flip Chip packaging structures have come together into what is being called Fan Out Packaging. These packages are for both low density and high density, Mobile and server applications. They have higher levels of integration and sophistication than has ever been possible in the past. An overview of the concept of Fan Out packaging, a history of its evolution, both low end and high end applications, and market trends will be included in this course.
John Hunt, ASE US, Inc. | John is Senior Director, Engineering, Technical Promotion, at ASE US Inc., and provides technical support for the Introduction, Engineering, Marketing, and Business Development activities for Advanced Wafer Level and Fan Out Packaging Technologies at ASE.
John has more than 40 years of experience in various areas of manufacturing, assembly and testing of electronic components and systems, with emphasis on the development of new technologies and processes, with a B.S. from Rutgers and an M.S. from University of Central Florida.
Tutorial – Option 3: Introduction to Solder Flip Chip with an Emphasis on Cu Pillar
Tuesday, December 5| 9:00am-12:00pm
This tutorial course will provide a historical overview and background on Solder Flip Chip technology with an emphasis on Copper Pillar Flip Chip as well as short market perspective. Interconnect structure, process flows, materials and package integration process methods for evolving flip chip applications will be discussed in detail. The understanding the trade-offs between the traditional solder based flip chip and Copper Pillar is key in determining the silicon device layout and the type of design rules that can be leveraged for new products. As part of this course, the Solder Bump and Copper Pillar bump structure formation will be reviewed as well as multiple Cu Pillar flip chip attachment methods such as Mass Reflow and Thermo-Compression Non-Conductive Paste (TCNCP) bonding. Reliability aspects such as IMC formations and ways to address will also be covered as a key consideration for interconnect decisions. Current market trends have led to additional questions regarding the longevity of flip chip versus other competing technologies such as Fan Out Wafer Level Packaging (FOWLP) will also be reviewed as well as a comparison between technologies.
Mark Gerber, ASE US, Inc. | Mark Gerber is currently the Director of Engineering and Marketing for Flip Chip and Advanced Interconnect at ASE US Inc. Prior to joining ASE, Mark was a Senior Member of the Technical Staff at Texas Instruments where he was responsible for leading a development and NPI team to support World Wide CMOS Packaging up until 2013 where he subsequently focused on Analog Advanced R&D. Prior to TI, Mark supported various R&D and NPI activities at Motorola SPS and Maxim Integrated for 7 and 3 years respectively. Mark holds a Bachelor’s degree in Mechanical Engineering from Texas A&M University, has written +20 papers and holds over 32 semiconductor packaging patents.
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