2016 Tutorial Speakers

Tuesday, December 13 | 9:00am-12:00pm

Now that Fan-out wafer level packaging (FO-WLP) has matured, unique advanced FO-WLP structures have been developed. This course will cover these advanced structures of FO-WLP and potential application spaces, technology roadmaps, and benchmarking. The challenges of moving from 300mm FO-WLP to panel will also be discussed.

1.               Definitions and Advantages
2.               Advanced Applications
3.               Package Structures including Advanced FO technologies
4.               Technology Roadmap
5.               Panel Challenges
6.               Benchmarking

Engineers and managers responsible for advanced packaging development, package characterization, package quality, package reliability and package design should attend this course. Engineers and those in marketing and sales who supply equipment, materials, or services to the advanced packaging supply chain should also attend. Both newcomers and experienced practitioners are welcome, but it is recommended that you take the Introduction to Fan-Out Wafer Level Packaging course prior to taking this course.

Beth Keser, Qualcomm
Fan-Out Wafer Level Packaging Technology Manager, Qualcomm
Beth Keser is a recognized global leader in the semiconductor packaging industry with over 18 years of experience, received her B.S. degree in Materials Science and Engineering from Cornell University and her Ph.D. from the University of Illinois at Urbana-Champaign. Beth’s excellence in developing revolutionary electronic packages for semiconductor devices has resulted in 14 patents, 9 patents pending, and over 40 publications in the semiconductor industry. Based in San Diego, Beth leads the Fan-Out and Fan-In Wafer Level Packaging Technology Development and NPI Group at Qualcomm. Beth’s team has qualified over 50 products resulting in over 6 billion units shipped–technology consumers around the world enjoy in cell phones today. Beth is also an IEEE CPMT Distinguished Lecturer who chaired IEEE CPMT’s 2015 Electronic Component and Technology Conference.



Tuesday, December 13 | 9:00am-12:00pm

Today’s miniaturization and performance requirements result in the usage of high-density advanced packaging technologies, such as system-in-package (SIP), direct-chip-attach, chip-scale packaging (CSP), and ball-grid-arrays (BGA). Due to their physical access limitation, the complexity and cost associated with their test and diagnosis are considered major issues facing their use.

This course introduces comprehensive knowledge of electrical modeling and test solutions for 3D packages. We begin by a short tutorial on 3D packages including interposers and TSV. We then place particular emphasis on electrical modeling; test and debugging approaches for 3D packages for RF, bio, power and MEMS packages. Finally, we cover diagnosis and repair techniques for assembled packages.

Bruce Kim, City University of New York
Bruce Kim is a professor of the Department of Electrical Engineering at City University of New York. He has about 300 publications in packaging and testing areas. He has instructed previous PDCs at IMAPS, IEEE EPTC and ECTC conferences. He is a Fellow of IMAPS and received the IMAPS Outstanding Educator award in 2012. He has also been a student chapter advisor. His research interests are in 3D passive components modeling and testing.


Conference Speakers

Conference Speakers

VIEW THE PROGRAM for full presentation and speaker listings.

3D ASIP 2016 Speaker Details/BIOs coming soon to this page